diff options
| author | Tero Kristo <t-kristo@ti.com> | 2015-11-30 15:43:25 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-11-30 20:34:17 +0100 |
| commit | 07ff73a932b725b2a4675bd0cc1a86b4933e433e (patch) | |
| tree | da9e26ac88590535060e130e8ce51c4369a7c2a8 /include | |
| parent | clk: qcom: msm8916: Move xo and sleep clocks into DT (diff) | |
| download | linux-07ff73a932b725b2a4675bd0cc1a86b4933e433e.tar.xz linux-07ff73a932b725b2a4675bd0cc1a86b4933e433e.zip | |
clk: ti: omap5+: dpll: implement errata i810
Errata i810 states that DPLL controller can get stuck while transitioning
to a power saving state, while its M/N ratio is being re-programmed.
As a workaround, before re-programming the M/N ratio, SW has to ensure
the DPLL cannot start an idle state transition. SW can disable DPLL
idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
active by setting a dependent clock domain in SW_WKUP.
This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/clk/ti.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 223be696df27..75205df29b9c 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -286,6 +286,7 @@ struct ti_clk_features { #define TI_CLK_DPLL_HAS_FREQSEL BIT(0) #define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) #define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) +#define TI_CLK_ERRATA_I810 BIT(3) void ti_clk_setup_features(struct ti_clk_features *features); const struct ti_clk_features *ti_clk_get_features(void); |