diff options
| author | Mike Habeck <habeck@sgi.com> | 2007-04-06 19:04:39 +0200 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2007-04-07 00:38:12 +0200 |
| commit | 2e0d232bff31973f58c33412b45fce51b6770698 (patch) | |
| tree | b23f921ec8786904b56e2b6c2c42822630757cb4 /include | |
| parent | [IA64] Fix CPU freq displayed in /proc/cpuinfo (diff) | |
| download | linux-2e0d232bff31973f58c33412b45fce51b6770698.tar.xz linux-2e0d232bff31973f58c33412b45fce51b6770698.zip | |
[IA64] SGI Altix : fix pcibr_dmamap_ate32() bug
On a SGI Altix TIOCP based PCI bus we need to include the ATE_PIO attribute
bit if we're mapping a 32bit MSI address.
Signed-off-by: Mike Habeck <habeck@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ia64/sn/pcibr_provider.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h index 17cb6cc3f21a..da205b7cdaac 100644 --- a/include/asm-ia64/sn/pcibr_provider.h +++ b/include/asm-ia64/sn/pcibr_provider.h @@ -21,6 +21,7 @@ #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \ asic == PCIIO_ASIC_TYPE_TIOCP) #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) +#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP) /* @@ -53,8 +54,8 @@ * Bridge PMU Address Transaltion Entry Attibutes */ #define PCI32_ATE_V (0x1 << 0) -#define PCI32_ATE_CO (0x1 << 1) -#define PCI32_ATE_PREC (0x1 << 2) +#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */ +#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */ #define PCI32_ATE_MSI (0x1 << 2) #define PCI32_ATE_PREF (0x1 << 3) #define PCI32_ATE_BAR (0x1 << 4) |