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author | Arnd Bergmann <arnd@arndb.de> | 2013-06-21 15:00:24 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2013-06-21 15:00:24 +0200 |
commit | e8f2ca97151892ab723dd8317313063cef79839d (patch) | |
tree | 147047c432e3af4cad25b4672b493b93edc32844 /include | |
parent | Merge tag 'renesas-cleanup-for-v3.11' of git://git.kernel.org/pub/scm/linux/k... (diff) | |
parent | ARM: EXYNOS: extend soft-reset support for EXYNOS5420 (diff) | |
download | linux-e8f2ca97151892ab723dd8317313063cef79839d.tar.xz linux-e8f2ca97151892ab723dd8317313063cef79839d.zip |
Merge tag 'soc-exynos5420-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/late
From Kukjin Kim:
based on tags/common-clk-audio
- add support for exynos5420 SoC
* tag 'soc-exynos5420-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: extend soft-reset support for EXYNOS5420
ARM: EXYNOS: add secondary CPU boot base location for EXYNOS5420
clocksource: exynos_mct: use (request/free)_irq calls for local timer registration
ARM: dts: Add initial device tree support for EXYNOS5420
clk: exynos5420: register clocks using common clock framework
ARM: EXYNOS: use four additional chipid bits to identify EXYNOS family
serial: samsung: select EXYNOS specific driver data if ARCH_EXYNOS is defined
ARM: EXYNOS: Add support for EXYNOS5420 SoC
ARM: dts: list the CPU nodes for EXYNOS5250
ARM: dts: fork out common EXYNOS5 nodes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/clk/exynos-audss-clk.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h new file mode 100644 index 000000000000..8279f427c60f --- /dev/null +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -0,0 +1,25 @@ +/* + * This header provides constants for Samsung audio subsystem + * clock controller. + * + * The constants defined in this header are being used in dts + * and exynos audss driver. + */ + +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H + +#define EXYNOS_MOUT_AUDSS 0 +#define EXYNOS_MOUT_I2S 1 +#define EXYNOS_DOUT_SRP 2 +#define EXYNOS_DOUT_AUD_BUS 3 +#define EXYNOS_DOUT_I2S 4 +#define EXYNOS_SRP_CLK 5 +#define EXYNOS_I2S_BUS 6 +#define EXYNOS_SCLK_I2S 7 +#define EXYNOS_PCM_BUS 8 +#define EXYNOS_SCLK_PCM 9 + +#define EXYNOS_AUDSS_MAX_CLKS 10 + +#endif |