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authorJamie Lenehan <lenehan@twibble.org>2006-09-27 08:05:39 +0200
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 08:05:39 +0200
commita09749dd86e9e93de10f12ab4ce4e90815b5650a (patch)
tree013d7deabb31dea70063a2acdc50ee86fb3c7b9a /include
parentsh: BSS init bugfix and barrier in entry point. (diff)
downloadlinux-a09749dd86e9e93de10f12ab4ce4e90815b5650a.tar.xz
linux-a09749dd86e9e93de10f12ab4ce4e90815b5650a.zip
sh: Titan board support.
Add support for the titan board. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-sh/titan.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h
new file mode 100644
index 000000000000..270a4f4bc8a9
--- /dev/null
+++ b/include/asm-sh/titan.h
@@ -0,0 +1,43 @@
+/*
+ * Platform defintions for Titan
+ */
+
+#ifndef _ASM_SH_TITAN_TITAN_H
+#define _ASM_SH_TITAN_TITAN_H
+
+#define __IO_PREFIX titan
+#include <asm/io_generic.h>
+
+/* IRQ assignments */
+#define TITAN_IRQ_WAN 2 /* eth0 (WAN) */
+#define TITAN_IRQ_LAN 5 /* eth1 (LAN) */
+#define TITAN_IRQ_MPCIA 8 /* mPCI A */
+#define TITAN_IRQ_MPCIB 11 /* mPCI B */
+#define TITAN_IRQ_USB 11 /* USB */
+
+/*
+ * The external interrupt lines, these take up ints 0 - 15 inclusive
+ * depending on the priority for the interrupt. In fact the priority
+ * is the interrupt :-)
+ */
+#define IRL0_IRQ 0
+#define IRL0_IPR_ADDR INTC_IPRD
+#define IRL0_IPR_POS 3
+#define IRL0_PRIORITY 8
+
+#define IRL1_IRQ 1
+#define IRL1_IPR_ADDR INTC_IPRD
+#define IRL1_IPR_POS 2
+#define IRL1_PRIORITY 8
+
+#define IRL2_IRQ 2
+#define IRL2_IPR_ADDR INTC_IPRD
+#define IRL2_IPR_POS 1
+#define IRL2_PRIORITY 8
+
+#define IRL3_IRQ 3
+#define IRL3_IPR_ADDR INTC_IPRD
+#define IRL3_IPR_POS 0
+#define IRL3_PRIORITY 8
+
+#endif