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authorStephen Boyd <sboyd@kernel.org>2020-12-21 02:17:51 +0100
committerStephen Boyd <sboyd@kernel.org>2020-12-21 02:17:51 +0100
commitb53a1603b46c5ee9b2fd4b276b12b916b33dc3d7 (patch)
treed761bed5a5fa1e1be707a1a3b241539a99e97f93 /include
parentMerge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-... (diff)
parentclk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs (diff)
parentclk: axi-clkgen: move the OF table at the bottom of the file (diff)
parentclk: Trace clk_set_rate() "range" functions (diff)
parentclk: at91: sam9x60: remove atmel,osc-bypass support (diff)
parentclk: si5351: Wait for bit clear after PLL reset (diff)
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linux-b53a1603b46c5ee9b2fd4b276b12b916b33dc3d7.zip
Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silabs' into clk-next
- Add some trace points for clk_set_rate() "range" functions - DVFS support for AT91 clk driver * clk-ti: clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs clk: ti: Fix memleak in ti_fapll_synth_setup * clk-analog: clk: axi-clkgen: move the OF table at the bottom of the file clk: axi-clkgen: wrap limits in a struct and keep copy on the state object dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format * clk-trace: clk: Trace clk_set_rate() "range" functions * clk-at91: clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error * clk-silabs: clk: si5351: Wait for bit clear after PLL reset