diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-10 10:18:29 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-11 22:21:22 +0200 |
| commit | 5f775498bdc44f294c37eaa7a205335e3b6667df (patch) | |
| tree | c6f015755676ae4d12731a587aef7b654dbcec0f /include | |
| parent | clk: qcom: add clocks necessary for apq8064 sdcc (diff) | |
| download | linux-5f775498bdc44f294c37eaa7a205335e3b6667df.tar.xz linux-5f775498bdc44f294c37eaa7a205335e3b6667df.zip | |
clk: qcom: Fully support apq8064 global clock control
Add in the handful of new clocks and introduce a new reset table
with the few new resets.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-msm8960.h | 11 | ||||
| -rw-r--r-- | include/dt-bindings/reset/qcom,gcc-msm8960.h | 16 |
2 files changed, 27 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h index f9f547146a15..7d20eedfee98 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8960.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h @@ -308,5 +308,16 @@ #define PLL13 292 #define PLL14 293 #define PLL14_VOTE 294 +#define USB_HS3_H_CLK 295 +#define USB_HS3_XCVR_SRC 296 +#define USB_HS3_XCVR_CLK 297 +#define USB_HS4_H_CLK 298 +#define USB_HS4_XCVR_SRC 299 +#define USB_HS4_XCVR_CLK 300 +#define SATA_PHY_CFG_CLK 301 +#define SATA_A_CLK 302 +#define CE3_SRC 303 +#define CE3_CORE_CLK 304 +#define CE3_H_CLK 305 #endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h index 07edd0e65eed..47c8686955da 100644 --- a/include/dt-bindings/reset/qcom,gcc-msm8960.h +++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h @@ -114,5 +114,21 @@ #define SFAB_SMPSS_S_RESET 97 #define PRNG_RESET 98 #define RIVA_RESET 99 +#define USB_HS3_RESET 100 +#define USB_HS4_RESET 101 +#define CE3_RESET 102 +#define PCIE_EXT_PCI_RESET 103 +#define PCIE_PHY_RESET 104 +#define PCIE_PCI_RESET 105 +#define PCIE_POR_RESET 106 +#define PCIE_HCLK_RESET 107 +#define PCIE_ACLK_RESET 108 +#define CE3_H_RESET 109 +#define SFAB_CE3_M_RESET 110 +#define SFAB_CE3_S_RESET 111 +#define SATA_RESET 112 +#define CE3_SLEEP_RESET 113 +#define GSS_SLP_RESET 114 +#define GSS_RESET 115 #endif |