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| author | Thomas Gleixner <tglx@linutronix.de> | 2024-02-23 10:07:24 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-02-23 10:07:24 +0100 |
| commit | 129993da1bede32d5c605c46d4ff10384359d385 (patch) | |
| tree | cb182dd67f2593167ed75813087132f11d3b03ce /include | |
| parent | genirq/irqdomain: Don't call ops->select for DOMAIN_BUS_ANY tokens (diff) | |
| parent | irqchip/riscv-intc: Introduce Andes hart-level interrupt controller (diff) | |
| download | linux-129993da1bede32d5c605c46d4ff10384359d385.tar.xz linux-129993da1bede32d5c605c46d4ff10384359d385.zip | |
Merge tag 'irq-for-riscv-02-23-24' into irq/msi
Pick up RISCV INTC changes to handle conflicts with the AIA updates.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/soc/andes/irq.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h new file mode 100644 index 000000000000..edc3182d6e66 --- /dev/null +++ b/include/linux/soc/andes/irq.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __ANDES_IRQ_H +#define __ANDES_IRQ_H + +/* Andes PMU irq number */ +#define ANDES_RV_IRQ_PMOVI 18 +#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI +#define ANDES_SLI_CAUSE_BASE 256 + +/* Andes PMU related registers */ +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 +#define ANDES_CSR_SCOUNTEROF 0x9d4 + +#endif /* __ANDES_IRQ_H */ |