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author | Javier Martinez Canillas <javier.martinez@collabora.co.uk> | 2015-01-24 05:25:01 +0100 |
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committer | Kukjin Kim <kgene@kernel.org> | 2015-01-29 00:52:22 +0100 |
commit | 8856010029985ba4d63a8942deb7f9e780285dd2 (patch) | |
tree | b0f4c8c470d780021e31e5dd072e340a79bddf1d /include | |
parent | ARM: dts: reduce total RAM by 22 MiB for exynos5422-odroidxu3 (diff) | |
download | linux-8856010029985ba4d63a8942deb7f9e780285dd2.tar.xz linux-8856010029985ba4d63a8942deb7f9e780285dd2.zip |
clk: exynos5420: Add IDs for clocks used in DISP1 power domain
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:
ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)
Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/clock/exynos5420.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 8dc0913f1775..99da0d117a7d 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -204,6 +204,12 @@ #define CLK_MOUT_MAUDIO0 643 #define CLK_MOUT_USER_ACLK333 644 #define CLK_MOUT_SW_ACLK333 645 +#define CLK_MOUT_USER_ACLK200_DISP1 646 +#define CLK_MOUT_SW_ACLK200 647 +#define CLK_MOUT_USER_ACLK300_DISP1 648 +#define CLK_MOUT_SW_ACLK300 649 +#define CLK_MOUT_USER_ACLK400_DISP1 650 +#define CLK_MOUT_SW_ACLK400 651 /* divider clocks */ #define CLK_DOUT_PIXEL 768 |