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authorStephen Boyd <sboyd@kernel.org>2019-09-04 20:14:51 +0200
committerStephen Boyd <sboyd@kernel.org>2019-09-04 20:14:51 +0200
commit924a8c6edaed6152711975a06d5ce73b99c486f9 (patch)
tree0b4be4bd5091b398a875f5d0cc75245109bc8e6d /include
parentLinus 5.3-rc1 (diff)
parentclk: sunxi-ng: h6: Allow I2S to change parent rate (diff)
downloadlinux-924a8c6edaed6152711975a06d5ce73b99c486f9.tar.xz
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Merge tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clock changes from Maxime Ripard: A few patches to enable the V3 SoC and fix the i2s clock for the H6. * tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: h6: Allow I2S to change parent rate clk: sunxi-ng: v3s: add Allwinner V3 support clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add the missing PLL_DDR1
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/sun8i-v3s-ccu.h4
-rw-r--r--include/dt-bindings/reset/sun8i-v3s-ccu.h3
2 files changed, 7 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
index c0d5d5599c87..014ac6123d17 100644
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -104,4 +104,8 @@
#define CLK_MIPI_CSI 73
+/* Clocks not available on V3s */
+#define CLK_BUS_I2S0 75
+#define CLK_I2S0 76
+
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
index b58ef21a2e18..b6790173afd6 100644
--- a/include/dt-bindings/reset/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h
@@ -75,4 +75,7 @@
#define RST_BUS_UART1 50
#define RST_BUS_UART2 51
+/* Reset lines not available on V3s */
+#define RST_BUS_I2S0 52
+
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */