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authorMaxime Chevallier <maxime.chevallier@bootlin.com>2019-02-11 15:25:28 +0100
committerDavid S. Miller <davem@davemloft.net>2019-02-14 01:17:53 +0100
commitac3f5533343f6ec7fa24a27f0ae22bbfd27e0b23 (patch)
tree8d331b1509236d5bdf74e7f500d6b6682c2ec4d7 /include
parentnet: phy: Move of_set_phy_eee_broken to phy-core.c (diff)
downloadlinux-ac3f5533343f6ec7fa24a27f0ae22bbfd27e0b23.tar.xz
linux-ac3f5533343f6ec7fa24a27f0ae22bbfd27e0b23.zip
net: phy: Extract genphy_c45_pma_read_abilities from marvell10g
Marvell 10G PHY driver has a generic way of initializing the supported link modes by reading the PHY's C45 PMA abilities. This can be made generic, since these registers are part of the 802.3 specifications. This commit extracts the config_init link_mode initialization code from marvell10g and uses it to introduce the genphy_c45_pma_read_abilities function. Only PMA modes are read, it's still up to the caller to set the Pause parameters. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
-rw-r--r--include/linux/phy.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 1a1d93a2a906..177a330d84e5 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -1116,6 +1116,7 @@ int genphy_c45_read_pma(struct phy_device *phydev);
int genphy_c45_pma_setup_forced(struct phy_device *phydev);
int genphy_c45_an_disable_aneg(struct phy_device *phydev);
int genphy_c45_read_mdix(struct phy_device *phydev);
+int genphy_c45_pma_read_abilities(struct phy_device *phydev);
/* The gen10g_* functions are the old Clause 45 stub */
int gen10g_config_aneg(struct phy_device *phydev);