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authorMichael Turquette <mturquette@baylibre.com>2015-06-20 22:29:48 +0200
committerMichael Turquette <mturquette@baylibre.com>2015-06-20 22:29:48 +0200
commit2cd7b0432888ef2e1f8b54c1c6f8751e1e0e9b5e (patch)
tree8ecab6ac6ef54b4ccc7b93a6a079e72a6ff7d640 /include
parentMerge branch 'clk-exynos-cpu-clk' into clk-next (diff)
parentclk: tegra: Fix hda2codec_2x clock name for Tegra30 (diff)
downloadlinux-2cd7b0432888ef2e1f8b54c1c6f8751e1e0e9b5e.tar.xz
linux-2cd7b0432888ef2e1f8b54c1c6f8751e1e0e9b5e.zip
Merge tag 'tegra-for-4.2-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.2-rc1 This contains the EMC clock driver that's been exhaustively reviewed and tested. It also includes a change to the clock core that allows a clock provider to perform low-level reparenting of clocks. This is required by the EMC clock driver because the reparenting needs to be done at a very specific point in time during the EMC frequency switch.
Diffstat (limited to 'include')
-rw-r--r--include/linux/clk-provider.h1
-rw-r--r--include/soc/tegra/fuse.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6a24df64b0a0..78842f46f152 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -592,6 +592,7 @@ long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_p);
+void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
{
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index b5f7b5f8d008..b019e3465f11 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -56,6 +56,7 @@ struct tegra_sku_info {
};
u32 tegra_read_straps(void);
+u32 tegra_read_ram_code(void);
u32 tegra_read_chipid(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);