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| author | Atish Patra <atish.patra@wdc.com> | 2021-09-27 13:40:11 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-10-04 12:37:16 +0200 |
| commit | 3a9f66cb25e18a3eeca36c08d9f823a35b3ddc22 (patch) | |
| tree | a15be60b9addd26c0fde559d2f2a80cad0bda612 /include | |
| parent | RISC-V: KVM: Implement MMU notifiers (diff) | |
| download | linux-3a9f66cb25e18a3eeca36c08d9f823a35b3ddc22.tar.xz linux-3a9f66cb25e18a3eeca36c08d9f823a35b3ddc22.zip | |
RISC-V: KVM: Add timer functionality
The RISC-V hypervisor specification doesn't have any virtual timer
feature.
Due to this, the guest VCPU timer will be programmed via SBI calls.
The host will use a separate hrtimer event for each guest VCPU to
provide timer functionality. We inject a virtual timer interrupt to
the guest VCPU whenever the guest VCPU hrtimer event expires.
This patch adds guest VCPU timer implementation along with ONE_REG
interface to access VCPU timer state from user space.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/clocksource/timer-riscv.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/clocksource/timer-riscv.h b/include/clocksource/timer-riscv.h new file mode 100644 index 000000000000..d7f455754e60 --- /dev/null +++ b/include/clocksource/timer-riscv.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra <atish.patra@wdc.com> + */ + +#ifndef __TIMER_RISCV_H +#define __TIMER_RISCV_H + +#include <linux/types.h> + +extern void riscv_cs_get_mult_shift(u32 *mult, u32 *shift); + +#endif |