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| author | Bjorn Helgaas <bhelgaas@google.com> | 2019-01-02 22:31:08 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-01-02 22:31:08 +0100 |
| commit | 6a790bf0eac449c3b4dd844c2e799037531f6401 (patch) | |
| tree | 18718518fc302d8c3cea1ab810a52dee32a4bdc1 /include | |
| parent | Merge branch 'remotes/lorenzo/pci/amlogic' (diff) | |
| parent | MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entry (diff) | |
| download | linux-6a790bf0eac449c3b4dd844c2e799037531f6401.tar.xz linux-6a790bf0eac449c3b4dd844c2e799037531f6401.zip | |
Merge branch 'remotes/lorenzo/pci/dwc'
- Constify histb dw_pcie_host_ops structure (Julia Lawall)
- Support multiple power domains for imx6 (Leonard Crestez)
- Constify layerscape driver data (Stefan Agner)
- Update imx6 Kconfig to allow imx6 PCIe in imx7 kernel (Trent Piepho)
- Support armada8k GPIO reset (Baruch Siach)
- Support suspend/resume support on imx6 (Leonard Crestez)
- Don't hard-code DesignWare DBI/ATU offst (Stephen Warren)
- Skip i.MX6 PHY setup on i.MX7D (Andrey Smirnov)
- Remove Jianguo Sun from HiSilicon STB maintainers (Lorenzo Pieralisi)
* remotes/lorenzo/pci/dwc:
MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entry
PCI: dwc: Don't hard-code DBI/ATU offset
PCI: imx: Add imx6sx suspend/resume support
PCI: armada8k: Add support for gpio controlled reset signal
PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7
PCI: dwc: layerscape: Constify driver data
PCI: imx: Add multi-pd support
dt-bindings: imx6q-pcie: Add multi-pd bindings for imx6sx
PCI: histb: Constify dw_pcie_host_ops structure
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index 6c1ad160ed87..c1b25f5e386d 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -440,6 +440,7 @@ #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30) +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) #define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0) #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) |