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authorMaciej W. Rozycki <macro@linux-mips.org>2008-05-27 22:19:51 +0200
committerIngo Molnar <mingo@elte.hu>2008-07-08 09:13:07 +0200
commit691874fa96d6349a8b60f8ea9c2bae52ece79941 (patch)
treea705c041eb25329632eab0491244b4544218273b /include
parentx86: I/O APIC: keep the timer IRQ masked during set-up (diff)
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x86: I/O APIC: timer through 8259A second-chance
Some systems incorrectly report the ExtINTA pin of the I/O APIC as the genuine target of the timer interrupt. Here is a change that copies timer pin information found to the other pin if one has been found only. This way both a direct and a through-8259A route is tested with the pin letting these problematic systems work well enough. If no timer pin information has been found for the I/O APIC, then local APIC variations are tried only, similarly to what is done without the change (except without the misleading messages). Obviously if we try the first-chance path without being told by the BIOS to do so, we should not complain either, so do not print the message in this case. The 64-bit variation should be updated with a call to replace_pin_at_irq() which can be done with the upcoming merge. Since add_pin_to_irq() is now always called in the first-chance path, the condition to require it in the second-chance path no longer happens. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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