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authorSimon Guo <wei.guo.simon@gmail.com>2018-05-23 09:02:01 +0200
committerPaul Mackerras <paulus@ozlabs.org>2018-06-01 02:30:10 +0200
commit5706340a339283fe60d55ddc72ee7728a571a834 (patch)
tree2f5c12185399ad0671cdb3baa0ca4360712aa0ab /ipc/Makefile
parentKVM: PPC: Book3S PR: Emulate mtspr/mfspr using active TM SPRs (diff)
downloadlinux-5706340a339283fe60d55ddc72ee7728a571a834.tar.xz
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KVM: PPC: Book3S PR: Always fail transactions in guest privileged state
Currently the kernel doesn't use transaction memory. And there is an issue for privileged state in the guest that: tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits without trapping into the PR host. So following code will lead to a false mfmsr result: tbegin <- MSR bits update to Transaction active. beq <- failover handler branch mfmsr <- still read MSR bits from magic page with transaction inactive. It is not an issue for non-privileged guest state since its mfmsr is not patched with magic page and will always trap into the PR host. This patch will always fail tbegin attempt for privileged state in the guest, so that the above issue is prevented. It is benign since currently (guest) kernel doesn't initiate a transaction. Test case: https://github.com/justdoitqd/publicFiles/blob/master/test_tbegin_pr.c Signed-off-by: Simon Guo <wei.guo.simon@gmail.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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