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| author | Mike Frysinger <michael.frysinger@analog.com> | 2007-11-21 09:08:58 +0100 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-11-21 09:08:58 +0100 |
| commit | 9e83b98a79d25136282a1757f879c40ee929a28b (patch) | |
| tree | 1ec7588320b7e95f05eab8b2f9a06c07f48034bc /ipc | |
| parent | Blackfin arch: cleanup BF54x header file and add BF547 definition (diff) | |
| download | linux-9e83b98a79d25136282a1757f879c40ee929a28b.tar.xz linux-9e83b98a79d25136282a1757f879c40ee929a28b.zip | |
Blackfin arch: add support for working around anomaly 05000312
Anomaly 05000312 - Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted:
DESCRIPTION:
When instruction cache is enabled, erroneous behavior may occur when any of the following instructions are interrupted:
. CSYNC
• SSYNC
• LCx =
• LTx = (only when LCx is non-zero)
• LBx = (only when LCx is non-zero)
When this problem occurs, a variety of incorrect things could happen, including an illegal instruction exception. Additional errors could
show up as an exception, a hardware error, or an instruction that is valid but different than the one that was expected.
WORKAROUND:
Place a cli before all SSYNC, CSYNC, "LCx =", "LTx =", and "LBx =" instructions to disable interrupts, and place an sti after each of these
instructions to re-enable interrupts. When these instructions are executed in code that is already non-interruptible, the problem will not
occur.
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'ipc')
0 files changed, 0 insertions, 0 deletions