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| author | Suresh Siddha <suresh.b.siddha@intel.com> | 2012-10-22 23:37:58 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2012-11-02 11:23:37 +0100 |
| commit | 279f1461432ccdec0b98c0bcbe0a8e2c0f6fdda5 (patch) | |
| tree | 1adaa912a846b6d45cff5c8b03db8f97d30ac779 /ipc | |
| parent | Merge git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending (diff) | |
| download | linux-279f1461432ccdec0b98c0bcbe0a8e2c0f6fdda5.tar.xz linux-279f1461432ccdec0b98c0bcbe0a8e2c0f6fdda5.zip | |
x86: apic: Use tsc deadline for oneshot when available
If the TSC deadline mode is supported, LAPIC timer one-shot mode can be
implemented using IA32_TSC_DEADLINE MSR. An interrupt will be generated
when the TSC value equals or exceeds the value in the IA32_TSC_DEADLINE
MSR.
This enables us to skip the APIC calibration during boot. Also, in
xapic mode, this enables us to skip the uncached apic access to re-arm
the APIC timer.
As this timer ticks at the high frequency TSC rate, we use the
TSC_DIVISOR (32) to work with the 32-bit restrictions in the
clockevent API's to avoid 64-bit divides etc (frequency is u32 and
"unsigned long" in the set_next_event(), max_delta limits the next
event to 32-bit for 32-bit kernel).
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: venki@google.com
Cc: len.brown@intel.com
Link: http://lkml.kernel.org/r/1350941878.6017.31.camel@sbsiddha-desk.sc.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'ipc')
0 files changed, 0 insertions, 0 deletions