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authorAlexander Duyck <alexander.h.duyck@intel.com>2010-11-17 04:26:59 +0100
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2010-11-17 04:26:59 +0100
commit32aa77a4fc06bd1116f83c25bf0389a3e9b80533 (patch)
tree7672d5a6b428f6dfcd5a3c42984435a059c78385 /kernel/gcov
parentixgbe: reorder Tx cleanup so that if adapter will reset we don't rearm (diff)
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ixgbe: change vector numbering so that queues end up on correct CPUs
This changes the numbering scheme slightly. Previously the ordering was coming out like this: Rx-2 Rx-1 Rx-0 TxRx-0 Which would drop two queues on CPU 0. This change makes it so that the ordering is like this: Rx-3 Rx-2 Rx-1 TxRx-0 This means that each CPU will have it's own Rx queue, and only CPU 0 will have the Tx queue. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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