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authorClaudiu Beznea <claudiu.beznea@microchip.com>2020-07-22 09:38:14 +0200
committerStephen Boyd <sboyd@kernel.org>2020-07-24 11:18:47 +0200
commit35d06f74785cc8d108dcb1e3324b2404fb39df0b (patch)
treeccf33dc79ca03ac4563c4c3b0e678823f03e6e9c /kernel/range.c
parentclk: at91: sam9x60-pll: check fcore against ranges (diff)
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clk: at91: sam9x60-pll: use frac when setting frequency
In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") the fractional part of PLL wasn't set on registers but it was calculated and taken into account for determining div and mul (see sam9x60_pll_get_best_div_mul()). Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'kernel/range.c')
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