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authorDmitry Osipenko <digetx@gmail.com>2018-11-24 22:13:47 +0100
committerThierry Reding <treding@nvidia.com>2019-01-16 13:21:57 +0100
commitd8f584099271ce51b59a4c5cec0c0f72e638145e (patch)
treefb2f6a78fb3c067169b9acfe6075ed0999d6edd3 /kernel/sys.c
parentARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+ (diff)
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ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30
The DRAM refresh-interval is getting erroneously set to "1" on exiting from memory self-refreshing mode. The clobbered interval causes the "refresh request overflow timeout" error raised by the External Memory Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20, but EMC registers are not latched after exiting from self-refreshing mode on Tegra20 and hence refresh-interval is not altered until an event that causes registers latching happens. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'kernel/sys.c')
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