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authorKishon Vijay Abraham I <kishon@ti.com>2021-03-10 13:08:36 +0100
committerVinod Koul <vkoul@kernel.org>2021-03-30 20:03:18 +0200
commit7e52a39f1942b771213678c56002ce90a2f126d2 (patch)
tree97896eb0b6eb6584947df337c9bc2cf4f7957893 /kernel/trace
parentphy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel (diff)
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phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in wiz. However during cleanup, it removed only the MUX clock provider. Remove the DIVIDER clock provider here. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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