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authorCatalin Marinas <catalin.marinas@arm.com>2009-05-30 15:00:18 +0200
committerCatalin Marinas <catalin.marinas@arm.com>2009-05-30 15:00:18 +0200
commit85d6943af50537d3aec58b967ffbd3fec88453e9 (patch)
tree2033d95a7a57f792856cc08e1bd77f01386c5ed6 /lib/crc-ccitt.c
parentAdd core support for ARMv6/v7 big-endian (diff)
downloadlinux-85d6943af50537d3aec58b967ffbd3fec88453e9.tar.xz
linux-85d6943af50537d3aec58b967ffbd3fec88453e9.zip
Fix the VFP handling on the Feroceon CPU
This CPU generates synchronous VFP exceptions in a non-standard way - the FPEXC.EX bit set but without the FPSCR.IXE bit being set like in the VFP subarchitecture 1 or just the FPEXC.DEX bit like in VFP subarchitecture 2. The main problem is that the faulty instruction (which needs to be emulated in software) will be restarted several times (normally until a context switch disables the VFP). This patch ensures that the VFP exception is treated as synchronous. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Nicolas Pitre <nico@cam.org>
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