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authorKefeng Wang <wangkefeng.wang@huawei.com>2016-01-29 09:39:02 +0100
committerWei Xu <xuwei5@hisilicon.com>2016-02-25 14:15:58 +0100
commit6897db62bbb322124ee7a5ee527134cde76d4aa1 (patch)
tree2eab9f0af5736ddea43e17a70d5160c937fbcd0c /lib/debugobjects.c
parentarm64: dts: hip05: Add L2 cache topology (diff)
downloadlinux-6897db62bbb322124ee7a5ee527134cde76d4aa1.tar.xz
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arm64: dts: hip05: Use Cortex specific device node for pmu
Instead of using the generic armv8-pmuv3 compatibility, use the more specific Cortex A57 compatibility. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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