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authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>2013-12-16 13:06:55 +0100
committerRalf Baechle <ralf@linux-mips.org>2014-03-26 23:09:18 +0100
commit6ebda44f366478d1eea180d93154e7d97b591f50 (patch)
tree88a32637a7ad46a690692a3603b369c4f9485515 /lib/dec_and_lock.c
parentMIPS: asm: r4kcache: Add EVA cache flushing functions (diff)
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MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushes
When flushing the icache, make sure the address limit is correct so the appropriate 'cache' instruction will be used. This has no impact on cores operating in non-eva mode. However, when EVA is enabled, we ensure that 'cache' will be used instead of 'cachee'. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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