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author | Peter Zijlstra <peterz@infradead.org> | 2015-04-24 00:49:20 +0200 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2015-07-27 14:06:23 +0200 |
commit | b0d8003ef405c4148b703cdaab1171045c6c3bbd (patch) | |
tree | 8180046acd2fdb22e2a0a747c9018f7674be8729 /lib/digsig.c | |
parent | x86: Provide atomic_{or,xor,and} (diff) | |
download | linux-b0d8003ef405c4148b703cdaab1171045c6c3bbd.tar.xz linux-b0d8003ef405c4148b703cdaab1171045c6c3bbd.zip |
frv: Rewrite atomic implementation
Mostly complete rewrite of the FRV atomic implementation, instead of
using assembly files, use inline assembler.
The out-of-line CONFIG option makes a bit of a mess of things, but a
little CPP trickery gets that done too.
FRV already had the atomic logic ops but under a non standard name,
the reimplementation provides the generic names and provides the
intermediate form required for the bitops implementation.
The slightly inconsistent __atomic32_fetch_##op naming is because
__atomic_fetch_##op conlicts with GCC builtin functions.
The 64bit atomic ops use the inline assembly %Ln construct to access
the low word register (r+1), afaik this construct was not previously
used in the kernel and is completely undocumented, but I found it in
the FRV GCC code and it seems to work.
FRV had a non-standard definition of atomic_{clear,set}_mask() which
would work types other than atomic_t, the one user relying on that
(arch/frv/kernel/dma.c) got converted to use the new intermediate
form.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'lib/digsig.c')
0 files changed, 0 insertions, 0 deletions