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| author | Luis R. Rodriguez <lrodriguez@atheros.com> | 2009-10-19 08:33:34 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2009-10-30 21:50:36 +0100 |
| commit | c75724d1747230abdd37d0594ac5277b867befd4 (patch) | |
| tree | 76ba22226b25c46ed01016f33ce72b793d7ec3cf /lib/gen_crc32table.c | |
| parent | ath9k_hw: update register initialization/reset values for ar9271 (diff) | |
| download | linux-c75724d1747230abdd37d0594ac5277b867befd4.tar.xz linux-c75724d1747230abdd37d0594ac5277b867befd4.zip | |
ath9k_hw: change the way we initialize the pll for ar9271
We adjust the core clock for ar9271 to 117 MHz; this also
requires us to adjust the baud divider based on the targetted
baud rate.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'lib/gen_crc32table.c')
0 files changed, 0 insertions, 0 deletions