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| author | Andreas Herrmann <andreas.herrmann3@amd.com> | 2010-09-30 14:32:35 +0200 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2010-10-02 01:18:31 +0200 |
| commit | 3fdbf004c1706480a7c7fac3c9d836fa6df20d7d (patch) | |
| tree | 67c1d3c0fe55e01cdc8e509d03c6f5a100ddf10e /lib/lru_cache.c | |
| parent | Merge remote branch 'origin/x86/cpu' into x86/amd-nb (diff) | |
| download | linux-3fdbf004c1706480a7c7fac3c9d836fa6df20d7d.tar.xz linux-3fdbf004c1706480a7c7fac3c9d836fa6df20d7d.zip | |
x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs
Instead of adapting the CPU family check in amd_special_default_mtrr()
for each new CPU family assume that all new AMD CPUs support the
necessary bits in SYS_CFG MSR.
Tom2Enabled is architectural (defined in APM Vol.2).
Tom2ForceMemTypeWB is defined in all BKDGs starting with K8 NPT.
In pre K8-NPT BKDG this bit is reserved (read as zero).
W/o this adaption Linux would unnecessarily complain about bad MTRR
settings on every new AMD CPU family, e.g.
[ 0.000000] WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 4863MB of RAM.
Cc: stable@kernel.org # .32.x, .35.x
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100930123235.GB20545@loge.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'lib/lru_cache.c')
0 files changed, 0 insertions, 0 deletions