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authorMauro Lima <mauro.lima@eclypsium.com>2022-10-12 17:21:35 +0200
committerMark Brown <broonie@kernel.org>2022-10-13 14:01:37 +0200
commit6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 (patch)
treeaefb6073741de020f21d9d039982cc7442659276 /mm/cma_debug.c
parentspi: aspeed: Fix typo in mode_bits field for AST2600 platform (diff)
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spi: intel: Fix the offset to get the 64K erase opcode
According to documentation, the 64K erase opcode is located in VSCC range [16:23] instead of [8:15]. Use the proper value to shift the mask over the correct range. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
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