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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2017-12-09 14:59:15 +0100
committerVineet Gupta <vgupta@synopsys.com>2017-12-20 21:41:44 +0100
commita08c832f277d7a6f9d3b341a5d5df2f5576220d8 (patch)
tree904c7baed42e96d959eaaa26c943abf4b95ee0c8 /mm/gup_benchmark.c
parentARC: [plat-hsdk] Switch DisplayLink driver from fbdev to DRM (diff)
downloadlinux-a08c832f277d7a6f9d3b341a5d5df2f5576220d8.tar.xz
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ARC: [plat-hsdk]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to 1GHz. It will be applied at the core pll driver probing. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'mm/gup_benchmark.c')
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