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authorDave Airlie <airlied@redhat.com>2011-11-22 21:01:00 +0100
committerDave Airlie <airlied@redhat.com>2011-11-22 21:01:00 +0100
commitcdaeb578aca9e017deb0f55f1af8a94a4d63efb3 (patch)
tree07efda5c2e864250f7c945db540b0e8b2deca0c1 /mm/mmzone.c
parentdrm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS (diff)
parentdrm/i915: Fix inconsistent backlight level during disabled (diff)
downloadlinux-cdaeb578aca9e017deb0f55f1af8a94a4d63efb3.tar.xz
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Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux into drm-fixes
* 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux: (25 commits) drm/i915: Fix inconsistent backlight level during disabled drm, i915: Fix memory leak in i915_gem_busy_ioctl(). drm/i915: Use DPCD value for max DP lanes. drm/i915: Initiate DP link training only on the lanes we'll be using drm/i915: Remove trailing white space drm/i915: Try harder during dp pattern 1 link training drm/i915: Make DP prepare/commit consistent with DP dpms drm/i915: Let panel power sequencing hardware do its job drm/i915: Treat PCH eDP like DP in most places drm/i915: Remove link_status field from intel_dp structure drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control drm/i915: Module parameters using '-1' as default must be signed type drm/i915: Turn on another required clock gating bit on gen6. drm/i915: Turn on a required 3D clock gating bit on Sandybridge. drm/i915: enable cacheable objects on Ivybridge drm/i915: add constants to size fence arrays and fields drm/i915: Ivybridge still has fences! drm/i915: forcewake warning fixes in debugfs drm/i915: Fix object refcount leak on mmappable size limit error path. drm/i915: Use mode_config.mutex in ironlake_panel_vdd_work ...
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