diff options
| author | Sean Christopherson <sean.j.christopherson@intel.com> | 2020-05-02 06:32:30 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-05-13 18:15:10 +0200 |
| commit | f98c1e77127de7d9ff558570c25d02ef077df50f (patch) | |
| tree | 047dd57f09a83b3abf03ad2a179f804ca53e113a /net/core | |
| parent | KVM: nVMX: Unconditionally validate CR3 during nested transitions (diff) | |
| download | linux-f98c1e77127de7d9ff558570c25d02ef077df50f.tar.xz linux-f98c1e77127de7d9ff558570c25d02ef077df50f.zip | |
KVM: VMX: Add proper cache tracking for CR4
Move CR4 caching into the standard register caching mechanism in order
to take advantage of the availability checks provided by regs_avail.
This avoids multiple VMREADs and retpolines (when configured) during
nested VMX transitions as kvm_read_cr4_bits() is invoked multiple times
on each transition, e.g. when stuffing CR0 and CR3.
As an added bonus, this eliminates a kvm_x86_ops hook, saves a retpoline
on SVM when reading CR4, and squashes the confusing naming discrepancy
of "cache_reg" vs. "decache_cr4_guest_bits".
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Message-Id: <20200502043234.12481-7-sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'net/core')
0 files changed, 0 insertions, 0 deletions