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authorSwapnil Patel <Swapnil.Patel@amd.com>2023-03-01 20:33:33 +0100
committerAlex Deucher <alexander.deucher@amd.com>2023-03-07 21:57:13 +0100
commit2d99a7ec25cf456cd3680eb314d6454138e5aa64 (patch)
treee6b2b5db83adff8734b91e266ecf27efcec9d2dc /net/dccp
parentdrm/amd/pm: Enable ecc_info table support for smu v13_0_10 (diff)
downloadlinux-2d99a7ec25cf456cd3680eb314d6454138e5aa64.tar.xz
linux-2d99a7ec25cf456cd3680eb314d6454138e5aa64.zip
drm/amd/display: Update clock table to include highest clock setting
[Why] Currently, the clk manager matches SocVoltage with voltage from fused settings (dfPstate clock table). And then corresponding clocks are selected. However in certain situations, this leads to clk manager not including at least one entry with highest supported clock setting. [How] Update the clk manager to include at least one entry with highest supported clock setting. Reviewed-by: Pavle Kotarac <pavle.kotarac@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Swapnil Patel <Swapnil.Patel@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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