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author | Andrew Murray <andrew.murray@arm.com> | 2019-06-17 21:01:05 +0200 |
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committer | Marc Zyngier <marc.zyngier@arm.com> | 2019-07-05 14:56:22 +0200 |
commit | 80f393a23be68e2f8a0f74258d6155438c200bbd (patch) | |
tree | c07e0e47ad5c14a8cbfef8cfe9a0763faf153254 /net/llc/llc_input.c | |
parent | KVM: arm/arm64: Remove pmc->bitmask (diff) | |
download | linux-80f393a23be68e2f8a0f74258d6155438c200bbd.tar.xz linux-80f393a23be68e2f8a0f74258d6155438c200bbd.zip |
KVM: arm/arm64: Support chained PMU counters
ARMv8 provides support for chained PMU counters, where an event type
of 0x001E is set for odd-numbered counters, the event counter will
increment by one for each overflow of the preceding even-numbered
counter. Let's emulate this in KVM by creating a 64 bit perf counter
when a user chains two emulated counters together.
For chained events we only support generating an overflow interrupt
on the high counter. We use the attributes of the low counter to
determine the attributes of the perf event.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'net/llc/llc_input.c')
0 files changed, 0 insertions, 0 deletions