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authorMiaoqing Pan <miaoqing@qca.qualcomm.com>2014-11-06 06:22:23 +0100
committerJohn W. Linville <linville@tuxdriver.com>2014-11-11 22:24:18 +0100
commit4e6ce4dc7ce71d0886908d55129d5d6482a27ff9 (patch)
tree6f6dbb1181866103987a897801bb615223900072 /net/mac80211/iface.c
parentbrcmfmac: fix conversion of channel width 20MHZ_NOHT (diff)
downloadlinux-4e6ce4dc7ce71d0886908d55129d5d6482a27ff9.tar.xz
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ath9k: Fix RTC_DERIVED_CLK usage
Based on the reference clock, which could be 25MHz or 40MHz, AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550. But, when a chip reset is done, processing the initvals sets the register back to the default value. Fix this by moving the code in ath9k_hw_init_pll() to ar9003_hw_override_ini(). Also, do this override for AR9531. Cc: stable@vger.kernel.org Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'net/mac80211/iface.c')
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