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| author | Tan, Tee Min <tee.min.tan@intel.com> | 2022-11-08 03:08:11 +0100 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2022-11-10 03:35:15 +0100 |
| commit | dcea1a8107c04b9521dee1dd37971757a22db162 (patch) | |
| tree | 202a2b94ba78869890c116cfb105fb1a4ae6dc45 /net/mctp | |
| parent | net: cxgb3_main: disable napi when bind qsets failed in cxgb_up() (diff) | |
| download | linux-dcea1a8107c04b9521dee1dd37971757a22db162.tar.xz linux-dcea1a8107c04b9521dee1dd37971757a22db162.zip | |
stmmac: intel: Update PCH PTP clock rate from 200MHz to 204.8MHz
Current Intel platform has an output of ~976ms interval
when probed on 1 Pulse-per-Second(PPS) hardware pin.
The correct PTP clock frequency for PCH GbE should be 204.8MHz
instead of 200MHz. PSE GbE PTP clock rate remains at 200MHz.
Fixes: 58da0cfa6cf1 ("net: stmmac: create dwmac-intel.c to contain all Intel platform")
Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
Signed-off-by: Tan, Tee Min <tee.min.tan@intel.com>
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Gan Yi Fang <yi.fang.gan@intel.com>
Link: https://lore.kernel.org/r/20221108020811.12919-1-yi.fang.gan@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'net/mctp')
0 files changed, 0 insertions, 0 deletions