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| author | Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> | 2020-06-29 14:00:53 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2020-06-29 15:18:00 +0200 |
| commit | 4a33bea003144e217d8a3ae666f171dfc2e97bd6 (patch) | |
| tree | 13089a517c27bdd3e448041fd6e463d45d0ba65d /net/rds/ib_frmr.c | |
| parent | dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY (diff) | |
| download | linux-4a33bea003144e217d8a3ae666f171dfc2e97bd6.tar.xz linux-4a33bea003144e217d8a3ae666f171dfc2e97bd6.zip | |
phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'net/rds/ib_frmr.c')
0 files changed, 0 insertions, 0 deletions