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| author | Fugang Duan <fugang.duan@nxp.com> | 2018-10-15 07:19:00 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-10-16 07:52:18 +0200 |
| commit | ec20a63aa8b8ec3223fb25cdb2a49f9f9dfda88c (patch) | |
| tree | 6eef69aee045c42bdc7c42933dc4f18369d6a4e8 /net/sctp/output.c | |
| parent | qed: fix spelling mistake "Ireelevant" -> "Irrelevant" (diff) | |
| download | linux-ec20a63aa8b8ec3223fb25cdb2a49f9f9dfda88c.tar.xz linux-ec20a63aa8b8ec3223fb25cdb2a49f9f9dfda88c.zip | |
net: fec: don't dump RX FIFO register when not available
Commit db65f35f50e0 ("net: fec: add support of ethtool get_regs") introduce
ethool "--register-dump" interface to dump all FEC registers.
But not all silicon implementations of the Freescale FEC hardware module
have the FRBR (FIFO Receive Bound Register) and FRSR (FIFO Receive Start
Register) register, so we should not be trying to dump them on those that
don't.
To fix it we create a quirk flag, FEC_QUIRK_HAS_RFREG, and check it before
dump those RX FIFO registers.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/sctp/output.c')
0 files changed, 0 insertions, 0 deletions