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| author | Joshua Yeong <joshua.yeong@starfivetech.com> | 2023-11-16 11:53:12 +0100 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2023-12-27 15:37:11 +0100 |
| commit | 6a902b118e7f30dbf0e6248f7b0f97e12c0939c3 (patch) | |
| tree | 80a620e91ca8a084954e4c99c014fcf28cd61252 /net/vmw_vsock | |
| parent | dt-bindings: timer: Add StarFive JH8100 clint (diff) | |
| download | linux-6a902b118e7f30dbf0e6248f7b0f97e12c0939c3.tar.xz linux-6a902b118e7f30dbf0e6248f7b0f97e12c0939c3.zip | |
clocksource/timer-riscv: Add riscv_clock_shutdown callback
Add clocksource detach/shutdown callback to disable RISC-V timer interrupt when
switching out riscv timer as clock source
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfivetech.com
Diffstat (limited to 'net/vmw_vsock')
0 files changed, 0 insertions, 0 deletions