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author | Alexander Kochetkov <al.kochet@gmail.com> | 2014-11-13 02:26:20 +0100 |
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committer | David S. Miller <davem@davemloft.net> | 2014-11-13 20:37:53 +0100 |
commit | 6ff53fd37175e35dc4f70b0e8f48b28338fbee29 (patch) | |
tree | 0e322b0185bec1710b17092092de85d3ebe19b3f /net | |
parent | net/smsc911x: Fix rare soft reset timeout issue due to PHY power-down mode (diff) | |
download | linux-6ff53fd37175e35dc4f70b0e8f48b28338fbee29.tar.xz linux-6ff53fd37175e35dc4f70b0e8f48b28338fbee29.zip |
net/smsc911x: Fix delays in the PHY enable/disable routines
Increased delay in the smsc911x_phy_disable_energy_detect (from 1ms to 2ms).
Dropped delays in the smsc911x_phy_enable_energy_detect (100ms and 1ms).
The patch affect SMSC LAN generation 4 chips with integrated PHY (LAN9221).
I saw problems with soft reset due to wrong udelay timings.
After I fixed udelay, I measured the time needed to bring integrated PHY
from power-down to operational mode (the time beetween clearing EDPWRDOWN
bit and soft reset complete event). I got 1ms (measured using ktime_get).
The value is equal to the current value (1ms) used in the
smsc911x_phy_disable_energy_detect. It is near the upper bound and in order
to avoid rare soft reset faults it is doubled (2ms).
I don't know official timing for bringing up integrated PHY as specs doesn't
clarify this (or may be I didn't found).
It looks safe to drop delays before and after setting EDPWRDOWN bit
(enable PHY power-down mode). I didn't saw any regressions with the patch.
The patch was reviewed by Steve Glendinning and Microchip Team.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Steve Glendinning <steve.glendinning@shawell.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
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