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| author | Geetha Sowjanya <geethasowjanya.akula@cavium.com> | 2017-06-23 15:34:36 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-06-23 18:58:04 +0200 |
| commit | f935448acf462c26142e8b04f1c8829b28d3b9d8 (patch) | |
| tree | 7516f4e4d39117e80be3b2859451725faded8271 /samples/pktgen | |
| parent | iommu/arm-smmu-v3: Enable ACPI based HiSilicon CMD_PREFETCH quirk(erratum 161... (diff) | |
| download | linux-f935448acf462c26142e8b04f1c8829b28d3b9d8.tar.xz linux-f935448acf462c26142e8b04f1c8829b28d3b9d8.zip | |
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
New named irq "combined" is set as a errata workaround, which allows to
share the irq line by register single irq handler for all the interrupts.
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>
[will: reworked irq equality checking and added SPI check]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'samples/pktgen')
0 files changed, 0 insertions, 0 deletions