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| author | Zhou Wang <wangzhou1@hisilicon.com> | 2021-12-07 07:32:48 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-12-15 11:14:06 +0100 |
| commit | 477436699e7801276fa7306e20318156cb535249 (patch) | |
| tree | ab9ab4db3a33551670af33bbb309849117f04325 /samples | |
| parent | iommu/io-pgtable-arm-v7s: Add error handle for page table allocation failure (diff) | |
| download | linux-477436699e7801276fa7306e20318156cb535249.tar.xz linux-477436699e7801276fa7306e20318156cb535249.zip | |
Revert "iommu/arm-smmu-v3: Decrease the queue size of evtq and priq"
The commit f115f3c0d5d8 ("iommu/arm-smmu-v3: Decrease the queue size of
evtq and priq") decreases evtq and priq, which may lead evtq/priq to be
full with fault events, e.g HiSilicon ZIP/SEC/HPRE have maximum 1024 queues
in one device, every queue could be binded with one process and trigger a
fault event. So let's revert f115f3c0d5d8.
In fact, if an implementation of SMMU really does not need so long evtq
and priq, value of IDR1_EVTQS and IDR1_PRIQS can be set to proper ones.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Acked-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/1638858768-9971-1-git-send-email-wangzhou1@hisilicon.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'samples')
0 files changed, 0 insertions, 0 deletions