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| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2018-09-05 13:09:54 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2018-09-11 15:47:38 +0200 |
| commit | 50ca031b51106b1b46162d4e9ecccb7edc95682f (patch) | |
| tree | b849a69a1a786a6fbc260de1159cd80b17a5aff5 /samples | |
| parent | MAINTAINERS: Add Gustavo Pimentel as DesignWare PCI maintainer (diff) | |
| download | linux-50ca031b51106b1b46162d4e9ecccb7edc95682f.tar.xz linux-50ca031b51106b1b46162d4e9ecccb7edc95682f.zip | |
Revert "PCI: Add ACS quirk for Intel 300 series"
This reverts f154a718e6cc ("PCI: Add ACS quirk for Intel 300 series").
It turns out that erratum "PCH PCIe* Controller Root Port (ACSCTLR) Appear
As Read Only" has been fixed in 300 series chipsets, even though the
datasheet [1] claims otherwise. To make ACS work properly on 300 series
root ports, revert the faulty commit.
[1] https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/300-series-c240-series-chipset-pch-spec-update.pdf
Fixes: f154a718e6cc ("PCI: Add ACS quirk for Intel 300 series")
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org # v4.18+
Diffstat (limited to 'samples')
0 files changed, 0 insertions, 0 deletions