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authorMasahiro Yamada <masahiroy@kernel.org>2020-02-01 17:49:24 +0100
committerMasahiro Yamada <masahiroy@kernel.org>2020-02-03 17:53:07 +0100
commit5f2fb52fac15a8a8e10ce020dd532504a8abfc4e (patch)
tree973fd15d54c102d120ff9e50d87d60b40cbc70db /scripts/Makefile.build
parentkbuild: fix the document to use extra-y for vmlinux.lds (diff)
downloadlinux-5f2fb52fac15a8a8e10ce020dd532504a8abfc4e.tar.xz
linux-5f2fb52fac15a8a8e10ce020dd532504a8abfc4e.zip
kbuild: rename hostprogs-y/always to hostprogs/always-y
In old days, the "host-progs" syntax was used for specifying host programs. It was renamed to the current "hostprogs-y" in 2004. It is typically useful in scripts/Makefile because it allows Kbuild to selectively compile host programs based on the kernel configuration. This commit renames like follows: always -> always-y hostprogs-y -> hostprogs So, scripts/Makefile will look like this: always-$(CONFIG_BUILD_BIN2C) += ... always-$(CONFIG_KALLSYMS) += ... ... hostprogs := $(always-y) $(always-m) I think this makes more sense because a host program is always a host program, irrespective of the kernel configuration. We want to specify which ones to compile by CONFIG options, so always-y will be handier. The "always", "hostprogs-y", "hostprogs-m" will be kept for backward compatibility for a while. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Diffstat (limited to 'scripts/Makefile.build')
-rw-r--r--scripts/Makefile.build8
1 files changed, 5 insertions, 3 deletions
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index a562d695f0fa..a1730d42e5f3 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -16,6 +16,8 @@ obj-m :=
lib-y :=
lib-m :=
always :=
+always-y :=
+always-m :=
targets :=
subdir-y :=
subdir-m :=
@@ -44,7 +46,7 @@ include $(kbuild-file)
include scripts/Makefile.lib
# Do not include host rules unless needed
-ifneq ($(hostprogs-y)$(hostprogs-m)$(hostlibs-y)$(hostlibs-m)$(hostcxxlibs-y)$(hostcxxlibs-m),)
+ifneq ($(hostprogs)$(hostlibs-y)$(hostlibs-m)$(hostcxxlibs-y)$(hostcxxlibs-m),)
include scripts/Makefile.host
endif
@@ -348,7 +350,7 @@ $(obj)/%.o: $(src)/%.S $(objtool_dep) FORCE
$(call if_changed_rule,as_o_S)
targets += $(filter-out $(subdir-obj-y), $(real-obj-y)) $(real-obj-m) $(lib-y)
-targets += $(extra-y) $(MAKECMDGOALS) $(always)
+targets += $(extra-y) $(always-y) $(MAKECMDGOALS)
# Linker scripts preprocessor (.lds.S -> .lds)
# ---------------------------------------------------------------------------
@@ -490,7 +492,7 @@ else
__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \
$(if $(KBUILD_MODULES),$(obj-m) $(mod-targets) $(modorder-target)) \
- $(subdir-ym) $(always)
+ $(subdir-ym) $(always-y)
@:
endif