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| author | Dmitry Osipenko <digetx@gmail.com> | 2021-06-01 04:31:19 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-06-02 10:58:55 +0200 |
| commit | 029f7e24a65df641ac843cda8dabe359ff0826eb (patch) | |
| tree | 80d9fee4e0dc803b899bcd01b448875e402240c7 /scripts/stackdelta | |
| parent | soc/tegra: pmc: Add driver state syncing (diff) | |
| download | linux-029f7e24a65df641ac843cda8dabe359ff0826eb.tar.xz linux-029f7e24a65df641ac843cda8dabe359ff0826eb.zip | |
soc/tegra: regulators: Support core domain state syncing
The core voltage shall not drop until state of core domain is synced,
i.e. all device drivers that use core domain are loaded and ready.
Support core domain state syncing. The core domain driver invokes the
core-regulator voltage syncing once the state of domain is synced, at
this point the core voltage is allowed to go lower than the level left
after bootloader.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
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