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author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-05-22 18:56:00 +0200 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-05-22 18:56:00 +0200 |
commit | 0bfbc914d9433d8ac2763a9ce99ce7721ee5c8e0 (patch) | |
tree | ffcb63ac983a005728f7d4fd244bc32ec66d9b16 /scripts | |
parent | Merge tag 'loongarch-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/c... (diff) | |
parent | riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800 (diff) | |
download | linux-0bfbc914d9433d8ac2763a9ce99ce7721ee5c8e0.tar.xz linux-0bfbc914d9433d8ac2763a9ce99ce7721ee5c8e0.zip |
Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Add byte/half-word compare-and-exchange, emulated via LR/SC loops
- Support for Rust
- Support for Zihintpause in hwprobe
- Add PR_RISCV_SET_ICACHE_FLUSH_CTX prctl()
- Support lockless lockrefs
* tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800
riscv: select ARCH_HAS_FAST_MULTIPLIER
riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required
riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_init
riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabled
riscv: mm: Always use an ASID to flush mm contexts
riscv: mm: Preserve global TLB entries when switching contexts
riscv: mm: Make asid_bits a local variable
riscv: mm: Use a fixed layout for the MM context ID
riscv: mm: Introduce cntx2asid/cntx2version helper macros
riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
riscv: mm: Combine the SMP and UP TLB flush code
riscv: Only send remote fences when some other CPU is online
riscv: mm: Broadcast kernel TLB flushes only when needed
riscv: Use IPIs for remote cache/TLB flushes by default
riscv: Factor out page table TLB synchronization
riscv: Flush the instruction cache during SMP bringup
riscv: hwprobe: export Zihintpause ISA extension
riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code
...
Diffstat (limited to 'scripts')
-rw-r--r-- | scripts/generate_rust_target.rs | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs index d30f61251ab0..641b713a033a 100644 --- a/scripts/generate_rust_target.rs +++ b/scripts/generate_rust_target.rs @@ -150,6 +150,12 @@ fn main() { // `llvm-target`s are taken from `scripts/Makefile.clang`. if cfg.has("ARM64") { panic!("arm64 uses the builtin rustc aarch64-unknown-none target"); + } else if cfg.has("RISCV") { + if cfg.has("64BIT") { + panic!("64-bit RISC-V uses the builtin rustc riscv64-unknown-none-elf target"); + } else { + panic!("32-bit RISC-V is an unsupported architecture"); + } } else if cfg.has("X86_64") { ts.push("arch", "x86_64"); ts.push( |