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authorJohannes Berg <johannes@sipsolutions.net>2006-06-21 15:42:43 +0200
committerJaroslav Kysela <perex@suse.cz>2006-06-22 21:34:38 +0200
commitf3d9478b2ce468c3115b02ecae7e975990697f15 (patch)
tree8397671cbf251c54bf539016468164e08d0c45ee /sound/aoa/soundbus/i2sbus/i2sbus-control.h
parent[ALSA] hda-codec - Use 3stack model for ASUS P5RD2-VM / P5GPL-X SE (diff)
downloadlinux-f3d9478b2ce468c3115b02ecae7e975990697f15.tar.xz
linux-f3d9478b2ce468c3115b02ecae7e975990697f15.zip
[ALSA] snd-aoa: add snd-aoa
This large patch adds all of snd-aoa. Consisting of many modules, it currently replaces snd-powermac for all layout-id based machines and handles many more (for example new powerbooks and powermacs with digital output that previously couldn't be used at all). It also has support for all layout-IDs that Apple has (judging from their Info.plist file) but not all are tested. The driver currently has 2 known regressions over snd-powermac: * it doesn't handle powermac 7,2 and 7,3 * it doesn't have a DRC control on snapper-based machines I will fix those during the 2.6.18 development cycle. Signed-off-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/aoa/soundbus/i2sbus/i2sbus-control.h')
-rw-r--r--sound/aoa/soundbus/i2sbus/i2sbus-control.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/sound/aoa/soundbus/i2sbus/i2sbus-control.h b/sound/aoa/soundbus/i2sbus/i2sbus-control.h
new file mode 100644
index 000000000000..bb05550f730b
--- /dev/null
+++ b/sound/aoa/soundbus/i2sbus/i2sbus-control.h
@@ -0,0 +1,37 @@
+/*
+ * i2sbus driver -- bus register definitions
+ *
+ * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
+ *
+ * GPL v2, can be found in COPYING.
+ */
+#ifndef __I2SBUS_CONTROLREGS_H
+#define __I2SBUS_CONTROLREGS_H
+
+/* i2s control registers, at least what we know about them */
+
+#define __PAD(m,n) u8 __pad##m[n]
+#define _PAD(line, n) __PAD(line, n)
+#define PAD(n) _PAD(__LINE__, (n))
+struct i2s_control_regs {
+ PAD(0x38);
+ __le32 fcr0; /* 0x38 (unknown) */
+ __le32 cell_control; /* 0x3c (fcr1) */
+ __le32 fcr2; /* 0x40 (unknown) */
+ __le32 fcr3; /* 0x44 (fcr3) */
+ __le32 clock_control; /* 0x48 (unknown) */
+ PAD(4);
+ /* total size: 0x50 bytes */
+} __attribute__((__packed__));
+
+#define CTRL_CLOCK_CELL_0_ENABLE (1<<10)
+#define CTRL_CLOCK_CLOCK_0_ENABLE (1<<12)
+#define CTRL_CLOCK_SWRESET_0 (1<<11)
+#define CTRL_CLOCK_INTF_0_ENABLE (1<<13)
+
+#define CTRL_CLOCK_CELL_1_ENABLE (1<<17)
+#define CTRL_CLOCK_CLOCK_1_ENABLE (1<<18)
+#define CTRL_CLOCK_SWRESET_1 (1<<19)
+#define CTRL_CLOCK_INTF_1_ENABLE (1<<20)
+
+#endif /* __I2SBUS_CONTROLREGS_H */