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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 19:24:21 +0200
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 19:24:21 +0200
commit8799ee9f49f6171fd58f4d64f8c067ca49006a5d (patch)
treeb746b8800bc99633f31505d151624c8ccd75cd47 /sound/mips
parent[ARM] 3666/1: TRIZEPS4 [1/5] core (diff)
downloadlinux-8799ee9f49f6171fd58f4d64f8c067ca49006a5d.tar.xz
linux-8799ee9f49f6171fd58f4d64f8c067ca49006a5d.zip
[ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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