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authorTakashi Iwai <tiwai@suse.de>2014-07-04 07:48:57 +0200
committerTakashi Iwai <tiwai@suse.de>2014-07-04 07:48:57 +0200
commit1a0e3f9639ebe7f0f17b40eb96d03c05ec067979 (patch)
tree55a007e8903e097cc1fee52dd17887b92d60c257 /sound/pci/hda/hda_intel.c
parentALSA: hda: Remove unused variable (diff)
parentALSA: hda - restore BCLK M/N value as per CDCLK for HSW/BDW display HDA contr... (diff)
downloadlinux-1a0e3f9639ebe7f0f17b40eb96d03c05ec067979.tar.xz
linux-1a0e3f9639ebe7f0f17b40eb96d03c05ec067979.zip
Merge branch 'for-linus' into for-next
Conflicts: sound/pci/hda/hda_intel.c
Diffstat (limited to 'sound/pci/hda/hda_intel.c')
-rw-r--r--sound/pci/hda/hda_intel.c50
1 files changed, 9 insertions, 41 deletions
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index dc0c8dac1900..75b52c4cd70d 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -61,9 +61,9 @@
#include <linux/vga_switcheroo.h>
#include <linux/firmware.h>
#include "hda_codec.h"
-#include "hda_i915.h"
#include "hda_controller.h"
#include "hda_priv.h"
+#include "hda_i915.h"
/* position fix mode */
enum {
@@ -333,22 +333,9 @@ static char *driver_short_names[] = {
[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
};
-
-/* Intel HSW/BDW display HDA controller Extended Mode registers.
- * EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
- * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
- * The values will be lost when the display power well is disabled.
- */
-#define AZX_REG_EM4 0x100c
-#define AZX_REG_EM5 0x1010
-
struct hda_intel {
struct azx chip;
- /* HSW/BDW display HDA controller to restore BCLK from CDCLK */
- unsigned int bclk_m;
- unsigned int bclk_n;
-
/* for pending irqs */
struct work_struct irq_pending_work;
@@ -777,22 +764,6 @@ static int param_set_xint(const char *val, const struct kernel_param *kp)
#define azx_del_card_list(chip) /* NOP */
#endif /* CONFIG_PM */
-static void haswell_save_bclk(struct azx *chip)
-{
- struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
-
- hda->bclk_m = azx_readw(chip, EM4);
- hda->bclk_n = azx_readw(chip, EM5);
-}
-
-static void haswell_restore_bclk(struct azx *chip)
-{
- struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
-
- azx_writew(chip, EM4, hda->bclk_m);
- azx_writew(chip, EM5, hda->bclk_n);
-}
-
#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
/*
* power management
@@ -820,12 +791,6 @@ static int azx_suspend(struct device *dev)
chip->irq = -1;
}
- /* Save BCLK M/N values before they become invalid in D3.
- * Will test if display power well can be released now.
- */
- if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
- haswell_save_bclk(chip);
-
if (chip->msi)
pci_disable_msi(chip->pci);
pci_disable_device(pci);
@@ -847,7 +812,7 @@ static int azx_resume(struct device *dev)
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
hda_display_power(true);
- haswell_restore_bclk(chip);
+ haswell_set_bclk(chip);
}
pci_set_power_state(pci, PCI_D0);
pci_restore_state(pci);
@@ -892,10 +857,9 @@ static int azx_runtime_suspend(struct device *dev)
azx_stop_chip(chip);
azx_enter_link_reset(chip);
azx_clear_irq_pending(chip);
- if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
- haswell_save_bclk(chip);
+ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
hda_display_power(false);
- }
+
return 0;
}
@@ -915,7 +879,7 @@ static int azx_runtime_resume(struct device *dev)
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
hda_display_power(true);
- haswell_restore_bclk(chip);
+ haswell_set_bclk(chip);
}
/* Read STATESTS before controller reset */
@@ -1604,6 +1568,10 @@ static int azx_first_init(struct azx *chip)
/* initialize chip */
azx_init_pci(chip);
+
+ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
+ haswell_set_bclk(chip);
+
azx_init_chip(chip, (probe_only[dev] & 2) == 0);
/* codec detection */