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authorJohn David Anglin <dave.anglin@bell.net>2016-11-25 02:18:14 +0100
committerHelge Deller <deller@gmx.de>2016-11-25 12:32:01 +0100
commit5035b230e7b67ac12691ed3b5495bbb617027b68 (patch)
tree8c293cf58ca0e05cc7ce78d9b47a3420c98c5ad5 /sound/ppc/powermac.c
parentparisc: Fix race in pci-dma.c (diff)
downloadlinux-5035b230e7b67ac12691ed3b5495bbb617027b68.tar.xz
linux-5035b230e7b67ac12691ed3b5495bbb617027b68.zip
parisc: Also flush data TLB in flush_icache_page_asm
This is the second issue I noticed in reviewing the parisc TLB code. The fic instruction may use either the instruction or data TLB in flushing the instruction cache. Thus, on machines with a split TLB, we should also flush the data TLB after setting up the temporary alias registers. Although this has no functional impact, I changed the pdtlb and pitlb instructions to consistently use the index register %r0. These instructions do not support integer displacements. Tested on rp3440 and c8000. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by: Helge Deller <deller@gmx.de>
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