diff options
| author | Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2021-03-26 23:16:19 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-03-31 19:00:38 +0200 |
| commit | 945b0b58c5d7c6640f9aad2096e4675bc7f5371c (patch) | |
| tree | e4e6b143c4462f07c749f2deac120fffbaa60370 /sound/soc/codecs/da732x.h | |
| parent | ASoC: lm49453: fix useless assignment before return (diff) | |
| download | linux-945b0b58c5d7c6640f9aad2096e4675bc7f5371c.tar.xz linux-945b0b58c5d7c6640f9aad2096e4675bc7f5371c.zip | |
ASoC: da732x: simplify code
cppcheck reports a false positive:
sound/soc/codecs/da732x.c:1161:25: warning: Either the condition
'indiv<0' is redundant or there is division by zero at line
1161. [zerodivcond]
fref = (da732x->sysclk / indiv);
^
sound/soc/codecs/da732x.c:1158:12: note: Assuming that condition
'indiv<0' is not redundant
if (indiv < 0)
^
sound/soc/codecs/da732x.c:1161:25: note: Division by zero
fref = (da732x->sysclk / indiv);
^
The code is awfully convoluted/confusing and can be simplified with a
single variable and the BIT macro.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20210326221619.949961-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/da732x.h')
| -rw-r--r-- | sound/soc/codecs/da732x.h | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/sound/soc/codecs/da732x.h b/sound/soc/codecs/da732x.h index c5af17ee1516..c2f784c3f359 100644 --- a/sound/soc/codecs/da732x.h +++ b/sound/soc/codecs/da732x.h @@ -48,14 +48,10 @@ #define DA732X_MCLK_20MHZ 20000000 #define DA732X_MCLK_40MHZ 40000000 #define DA732X_MCLK_54MHZ 54000000 -#define DA732X_MCLK_RET_0_10MHZ 0 -#define DA732X_MCLK_VAL_0_10MHZ 1 -#define DA732X_MCLK_RET_10_20MHZ 1 -#define DA732X_MCLK_VAL_10_20MHZ 2 -#define DA732X_MCLK_RET_20_40MHZ 2 -#define DA732X_MCLK_VAL_20_40MHZ 4 -#define DA732X_MCLK_RET_40_54MHZ 3 -#define DA732X_MCLK_VAL_40_54MHZ 8 +#define DA732X_MCLK_VAL_0_10MHZ 0 +#define DA732X_MCLK_VAL_10_20MHZ 1 +#define DA732X_MCLK_VAL_20_40MHZ 2 +#define DA732X_MCLK_VAL_40_54MHZ 3 #define DA732X_DAI_ID1 0 #define DA732X_DAI_ID2 1 #define DA732X_SRCCLK_PLL 0 |